The present invention relates to a semiconductor apparatus, in particular a semiconductor apparatus suitable for preventing the deterioration of the data processing performance.
As the semiconductor manufacturing process has been miniaturized, the scale of a circuit that can be mounted on one semiconductor chip is increasing. As a result, in logic LSIs, large number of functional blocks necessary for the system can be mounted on one semiconductor chip. Therefore, a larger number of data processes are carried out in a logic LSI. Because of this trend, it has been required to improve data transfer performance between a logic LSI and a memory and thereby improve the overall performance of the system.
Japanese Unexamined Patent Application Publication No. 2009-230792 discloses a solution for this requirement. A multi-port memory disclosed in Japanese Unexamined Patent Application Publication No. 2009-230792 includes a memory array that includes a plurality of memory cells disposed at intersections of a plurality of bit lines and a plurality of word lines and is divided into n memory banks (n is an integer equal to or greater than 2), m input/output ports (m is an integer equal to or greater than 2) that independently inputs/outputs a command, an address, and data from/to each of the memory banks, and a path switching circuit that arbitrarily sets a command signal path, an address signal path, and a data signal path between the memory banks and the input/output ports. The path switching circuit includes crossbar switches that set the connection state of each of the command signal line, the address signal line, and the data signal line between the memory banks and the input/output ports, and a broadcast switch unit that, in a broadcast mode, forms a path through which data read from one memory bank is output to a plurality of ports or data input from one port is written into a plurality of memory banks.
This multi-port memory further includes an arbitration circuit that, when access requests from two or more input/output ports to the same memory bank occur simultaneously in the normal operation state, accepts an access request from an input/output having a higher priority and prohibits the access request(s) from the remaining input/output port(s). In the broadcast mode, this arbitration circuit also prohibits, for example, accesses from input/output ports other than the input/output port from which the broadcast read command is input.
Further, Japanese Unexamined Patent Application Publication No. 57-208689 discloses a technique for independently driving a plurality of elements having a memory function by supplying independent clock signals to the plurality of elements having a memory function.